Sandy Bridge Times New Itanium: Eight Core 50MB Cache

With the approach of Sandy Bridge's new architecture, not only the desktop, mobile, and server sectors will be renewed, but also the next-generation Itanium processors for the mission-critical enterprise service market will draw some of their nutrition.

The schedule of the 2011 International Solid State Circuit Conference (ISSCC) to be held in February next year shows that Intel will introduce the next generation of Itanium products code-named "Poulson" for the first time. It is fabricated on a 32nm CMOS process, with 9 copper metal layers, 3.1 billion transistors, and a core area of ​​18.2 x 29.9 = 544.18 square millimeters, which clearly demonstrates that Intel has at least completed the overall design.

The new Itanium will have eight cores and support hyper-threading technology, that is, 16 logic cores, support up to 12-way instruction launch (12-Wide-Issue/currently only four launches on the desktop), on-chip cache total up to 50MB At the same time, the ring bus interconnection system is adopted, the peak bandwidth between the processors can reach 128 GB/s, the memory bandwidth is up to 45 GB/s, and a new instruction set may also be supported.

The latest products of the Itanium series are the Tukwila Itanium 9300 series released earlier this year, 65nm process manufacturing (45nm has been skipped), 2 billion transistors, four cores and eight threads, and three levels of cache up to 24MB, using the QPI interconnection bus and Supports standard DDR3 memory.

The new Itanium Sandy Bridge architecture is expected to be released in 2012, and then code-named Kittson, but without any specific information, do not know whether the production process will not enter the 22nm process again.

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