The timing performance of an FPGA design is determined by the physical device, user code design, and EDA software. Anything that is ignored will have a significant impact on timing performance. This section focuses on the optimal use of Xilinx physical devices and EDA software in large-scale designs.
1) IO constraint skillsGood design must consider the skills of IO constraints. For Xilinx devices, the carry chain is vertically distributed, and the logically arranged blocks also have a direct connection of the three-state buffer lines in the horizontal direction, and the hard core elements are basically distributed in columns (the shortest path in the horizontal direction) Therefore, the optimal solution is to place the I/O for the control signal on the top or bottom of the device and arrange it vertically; the I/O of the data bus is placed on the left and right sides of the device, and is horizontally arranged. As shown in Figure 5-16.
Figure 5-16 Schematic diagram of the best IO layout for Xilinx devices
This IO allocation takes full advantage of the Xilinx FPGA chip architecture features such as the carry chain arrangement and block RAM, hard multiplier locations. The structure of the carry chain is shown in Figure 5-17. It can solve the problem of multi-bit wide addition and multiply carry delay from the lowest bit to the highest bit; block RAM and hard multiplier can save a lot of logic resources and guarantee timing, both of which are top-down in FPGA chip. The strip distribution, so the data flow level, control flow vertical can maximize the use of the chip infrastructure. Of course, in the actual system design, the above requirements may not be fully realized, but it is still necessary to arrange high-speed, multi-bit wide signals on the left and right sides of the chip as much as possible.
Figure 5-17 Schematic diagram of the carry chain structure of Xilinx devices
2) ISE implementation toolsThe implementation tools integrated in ISE have different levels of effort (Effort Level), of course, using the highest level, can improve timing performance without having to take other measures (such as applying more advanced timing constraints, using advanced tools or changing code, etc.) But it takes a long calculation time. To this end, the best process recommended by Xilinx is shown in Figure 5-18.
Figure 5-18 The best use strategy for Xilinx implementation tools
In the first pass, use the global timing constraints and the default implementation parameters option. If the timing requirements are not met, try the following:
(1) Try to modify the code, such as using the appropriate code style, adding pipelines, etc.
(2) Modify the comprehensive parameter options, such as OpTImizaTIon Effort, Use Synthesis Constraints File, Keep Hierarchy, Register
DuplicaTIon, Register Balancing, etc.;
(3) Increase the level of effort to implement the tool;
(4) A method of specifying path timing constraints in synthesis and implementation.
The implementation tools are divided into two parts: mapping (MAP) and place and route (PAR). Like PAR, you can also use the Map-TIming parameter option to constrain the critical path. For example, the parameter "Timing-Driven Packing and Placement" gives priority to the critical path with priority timing constraints; user constraints are passed from the User Constraints File (UCF) to the design through the Translate process.
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