Heterogeneous Computing Architecture (HSA) will help achieve high-performance, low-power processor designs. As HSA standards and software solutions mature, processor developers will be able to leverage this technology to facilitate heterogeneous core interoperability within a system-on-a-chip (SoC) and distribute complex tasks to the most appropriate computing unit through software. Furthermore, high computational efficiency and low energy consumption are achieved.
The era of heterogeneous computing has finally arrived, which is just enough to save the processor designer from the new process cost increase of 28 nanometers (nm) that caters to Moore's Law. Instead of relying on expensive low-power transistors, processor designers can help reduce energy consumption by distributing system workloads to different heterogeneous computing units.
Industry giants work together to promote HSA technology
In recent years, the advancement of processor energy efficiency is mostly due to the rapid development of miniaturized semiconductor processes. With the innovation of manufacturing technology, the cost of each transistor is continuously increasing, and Heterogenous System Architecture (HSA), etc. Alternative technologies have therefore risen.
Unlike homogeneous processor architectures that rely on the same general-purpose central processing unit (CPU) core, HSAs connect multiple computing cores such as CPUs, graphics processing units (GPUs), digital signal processors (DSPs), and field-programmable gate arrays ( FPGAs and fixed-function hardware, etc., various cores are optimized for different types of application workloads.
The HSA Foundation, established by AMD, ARM, ImaginaTIon, MediaTek, Qualcomm, Samsung Electronics and Texas Instruments, aims to ensure applications The program manages application execution by assigning tasks to the Super Micro Generation Graphics Core (GCN) computing unit that has the highest power efficiency for a particular workload. The HSA Foundation has established an open standard for connecting heterogeneous computing cores, enabling companies to develop solutions that support common software infrastructure to enable heterogeneous applications with high performance and high power efficiency.
Support for x86/ARM architecture HSA to achieve cross-platform design
In early 2014, AMD Semiconductor announced the A-Series Acceleration Processor (APU), Kaveri, which supports HSA functions. Software vendors can use the system to design the software development tools needed to deploy HSA-enabled applications.
One of HSA's key features is the ability to support x86 products and secure international architecture products across platforms, as well as development systems for developing HSA Intermediate Language (HSAIL) compilers and other tools to facilitate true portable applications. After the initial public release of the HSA system architecture specification (tentatively version 1.0) in June 2014, more software development teams are now able to learn the details of HSA and develop new ones using the simpler HSA heterogeneous programming model. Power saving algorithm.
Since current system performance expansion is limited by power consumption, AMD has begun to develop a heterogeneous computing form that supports highly parallel tasks and can be seamlessly translated between CPU and GPU. This technological innovation forms the basis of HSA, bringing opportunities to enhance energy efficiency while improving efficiency and maintaining programmability. To integrate the CPU and GPU on the same chip, the key is the GPU design.
The work done per unit of energy consumption is a common energy efficiency indicator. For example, the more efficient a notebook computer, the less the battery can be used and the lower the heat level. In terms of operational computing, the United States Energy Star Program has developed a set of reasonable estimates for typical energy consumption; in particular, the standard is based on “short-term idle†power.
In general, after accessing a file or opening a web page, the user will take the time to view the results. Such idle periods may be as short as the interval between key inputs or between video frames in modern systems, during which time the processor enters a low power state. Therefore, AMD's ability to divide computing power by standard energy is defined as the general efficiency of its mobile device chips. For example, comparing two notebooks with similar performance, the user must prefer a model with longer battery life. Similarly, if two notebook computers with the same battery life are compared, the user will also tend to choose the one with higher performance and faster response speed. Both of these situations can be presented through standard use of energy efficiency indicators.
AMD plans to increase standard energy efficiency by a factor of 25 over the next six years, and has commissioned a market analyst firm, TIrias Research, to evaluate the target and to analyze the results of research conducted by AMD. Become a technical white paper published on the TIrias Research website.
In order to achieve such a positive goal of 25 times, AMD will use a wide range of resources, in addition to focusing on architecture, design and software, and will be supplemented by silicon wafer process technology. Specifically, AMD will focus on the following three areas:
. Intelligent Instant Power Management Improvement
These improvements help reduce idle power consumption and take advantage of the Fast to Idle that quickly completes the work to get back to a low-power state.
. Enhanced heterogeneous computing power
HSA can help APUs improve general workload performance (as shown by industry standards such as PCMark 8 v2.0) and emerging visually-oriented interactive workloads (such as natural user interfaces along with image and speech recognition).
. Innovation in high power efficiency implementation
Improve the efficiency of APU's intellectual property (IP) by applying technologies such as advanced power gating, low-voltage operation, and further integration of system components.
Tirias Research points out that it will reduce the power savings achieved by idle power consumption and intelligent power management, combined with heterogeneous performance improvements and program improvements. AMD Semiconductor should be able to achieve the goal of achieving 25 times the standard energy efficiency improvement between 2014 and 2020.
AMD currently integrates system components such as GPUs, memory controllers, input/output (I/O) controllers and peripheral busbars in a notebook computer into a single die, enabling simultaneous monitoring of the CPU and Precision power management for GPUs. This technology effectively balances power optimization between the two units, concentrating heat dissipation on the units that need the most heat. In addition, moving the GPU to the CPU die can reduce the number of memory interfaces required while also achieving power savings.
AMD's intelligent power management uses a dedicated die controller to track power consumption, temperature, and activity of major components, further enhancing the efficiency of the APU. This power microcontroller is like the command of the "APU Symphony", which directs the processing focus to the correct position at the right time. It can quickly respond to thermal events, and the controller can quickly distribute power to specific parts of the CPU to play. Maximum efficiency and efficiency. In addition, it is also possible to judge when each unit has the least activity and to reduce its operation to a minimum or completely shut it down.
If the processing component can complete its work in the shortest time and then enter the deepest sleep state, it will reach its maximum energy efficiency. This “accelerate into idle mode†behavior is useful for most consumer-oriented tasks such as web browsing, file editing, and photo editing. Coordinating the use of GPUs and CPUs enables the APU to complete tasks faster, then reduce power and reduce total energy consumption (energy = power x time). The transition time of this power consumption state should be extremely short, so that the unit can reduce the power as soon as possible, so that the processor can enter the idle state between the user's key input or the video frame.
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