Read the crowd of this article: familiar with the basic knowledge of digital circuits (such as adders, counters, RAM, etc.), familiar with the basic synchronous circuit design method, familiar with the HDL language, understand the structure of the FPGA, and understand the FPGA design process.
1. The benefits of FPGA
Design engineers do not need to draw cumbersome schematic PCB connections, thus shifting the focus of work to functional implementation, greatly improving the work efficiency; with the promotion of HDL (Hardware DescripTIon Language) hardware description language language synthesis tools and other related tools The application of FPGAs has been increased.
2. Some bad habits of engineers when using FPGA
Any business is divided into two, which has advantages and disadvantages.
We have found that more and more engineers are not concerned about their own circuit implementations, thinking that "I just have to describe the function correctly, and other things will be handed over to the tool."
Under the influence of this kind of thinking, when engineers describe the circuit in HDL language, there is no circuit concept in the head, or it is very vague; it is not clear what the code written by itself is, what it looks like when it is mapped into the chip. Are there any special resources that make full use of the FPGA? When encountering problems, the first thing that comes to mind is to change the FPGA device with faster speed and larger capacity, which leads to an increase in material cost. What is more terrible is that because the device structure is not understood, the design skills closely related to the device structure are not understood. Depending on the tools such as synthesis, if the tools are not working, they will be helpless, which will delay the problem, which will seriously affect the development cycle and lead to a sharp increase in development costs.
3. Learn the knowledge that FPGAs should have
At present, our design scale is getting bigger and bigger, and millions of doors and millions of gates are common. At the same time, the device technology we use is more and more advanced, and has entered the deep sub-micron era. In the treatment of deep sub-micron devices, our design methods will inevitably change, paying more attention to the line delays that were rarely noticed before (I believe, ASIC design will do so later).
If we don't improve our design methods and design skills, we can't face these huge circuit designs based on deep submicron technology. Moreover, the current competition is more and more motivating. From the perspective of saving company cost, we also require us to do more functions in a smaller device.
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