CMOS sensor, 3D release is one after another

In the ongoing "ISSCC 2016" (January 31-February 4, 2016, San Francisco, USA), the publication related to 3D (three-dimensional) of laminated CMOS image sensors has continued. In the "SESSION6 Image Sensors" forum with nine presentations, three presentations were related to the 3D of CMOS image sensors. In the past, the industry was trying to make 3D, and in addition to the higher cost and low power consumption, the three technologies were easily "modularized" in 3D.

Easily change the pixel count by modular means: TSMC (2016 IEEE International Solid-State Circuits Conference, 6.8: A 1.5V 33Mpixel 3D-Stacked CMOS Image Sensor with Negative Substrate Bias) (click to enlarge)

At the conference, TSMC gave a speech entitled "A 1.5V 33Mpixel 3D-Stacked CMOS Image Sensor with Negative Substrate Bias" (Paper 6.8) (see photo). The specific content is: when stacking CMOS image sensor chip and image processing circuit chip, it is necessary to deal with the voltage difference between the two, the voltage of the image processing circuit will be reduced to about 1V with the miniaturization, and the image sensor needs 2V. The left and right voltages, so the company tried to apply a negative bias to the substrate of the image sensor chip.

The company highlighted the related modular technology, which combines approximately 8.3 megapixel 4K image sensors into a single module like tiles, increasing the number of pixels without major design changes. This is achieved by a configuration in which the image processing circuit is superimposed on the image sensor chip instead of the two-dimensional configuration. In addition, the company has also made the image processing circuit chip have a rewiring layer function for the wiring for accessing each pixel, and in this respect, has been improved in the size of the image sensor chip.

At the time of lamination, the wiring layer side of the image sensor chip is bonded to the wiring layer side of the image processing circuit chip by using a back side illumination (BSI) type CMOS sensor. Among them, a high-cost TSV (silicon through electrode) is not used, and electrical bonding and insulation are achieved by adhesion. TSMC expects that the market for image sensor applications will be further expanded, so this opportunity will inform the potential customers that the company has the basic technology to meet the needs of a variety of applications.

Can contribute to low power by improving the read circuit

Toshiba gave a speech at the conference under the heading "A 1.2e- Temporal Noise 3D-Stacked CMOS Image Sensor with Comparator-Based Multiple-Sampling PGA" (Paper 6.7). Imagine using a smartphone as an application. This technology separately develops an image sensor chip and an image processing circuit chip and then performs lamination, thereby shortening the development period. The feature is that the read circuit uses a new low-power amplifier circuit and an AD converter. As Toshiba is in a very delicate period of development, the company did not clarify the business operation of related technologies in its speech.

In addition, at this conference, NHK Broadcasting Technology Research Institute, Brookman Technology, TSMC and Shizuoka University also featured "A 1.1μm 33Mpixel 240fps 3D-Stacked CMOS Image Sensor with 3-Stage Cyclic-Based Analog-to-Digital Converters". (Paper 6.9) gave a speech on the topic. The video camera for 8K TV content that has been put into practical use by NHK has been introduced, and how to make the image sensor equipped with the camera small and low-power is introduced. As with the technology published by TSMC, TSV is not used, but a technology in which a BSI type image sensor and an image processing circuit chip are bonded together is used.

This technique connects a signal composed of pixels of a pitch of 1.1 μm to the total wiring of the image processing circuit chip of the lower layer in units of 4 × 4 pixels. The AD converter of the read circuit is changed to a three-stage configuration, and an AD conversion method suitable for low power consumption is adopted on the premise of high-speed transmission. Specifically, the 1st to 2nd grades are cyclical, and the 3rd grades are successive approximations. By the way, the relevant publication pointed out that by working on 3D, wiring, and AD conversion circuits, it is possible to achieve 8 frames of images at 240 frames per second, but this time, for the purpose of publishing in the society, the best data is produced. . The NHK Institute of Technology said that it is not yet planned to promote the practical use of cameras for 8K TV content based on this standard.

At the meeting, Matsushita delivered three speeches. Two of them are related to organic film type image sensors.