• Design costs, complexity, and productivity will become even more thorny. • Design will increasingly require a variety of different timing scenarios. “SoC design is getting faster and faster.†Mr. Robert Smith, vice president of Marketing, Magma Design & Implementation Division Touchingly said, “In the case of Apple, they recently announced that they will launch the CDMA iPhone with the network operator Verizon in January 2011. In this way, since the launch of the first iPhone in January 2007, Apple has been A total of five different types of mobile phones were introduced during the year, and the functions of these mobile phones have been more complex than ever."
In an analysis table, the reporter saw the first iPhone-based platform clocked at 620MHz, with 128MbRAM, and has a 2 million-pixel camera and 3-axis accelerometer; and the iPhone 4 launched in 2010, the platform clock speed Has risen to 800MHz, RAM reached 512Mb, while having 30 frames per second HD video recording and 3-axis gyroscope / digital compass function. "I was very surprised to have so many features integrated in such a small package," said Robert Smith. "In order to integrate more features in a smaller area, advanced IC design companies have already turned to 32-nanometer and 28-nanometer technologies. At present, five advanced IC design companies are using Magma's tools to develop 28nm products, and the pressure facing IC design companies is conceivable."
The cost, complexity, and production efficiency of the chip are three things IC design companies typically face. Unfortunately, the development of these three factors at 32-nm, 28-nm, and smaller node designs has caused everyone to find it tricky. From a design cost point of view, the cost of a 32-nanometer chip design is around 70 million U.S. dollars. It will soar to 100 million U.S. dollars at 28 nanometers, and it will increase to 120 to 150 million U.S. dollars at 20 nanometers. At the same time, from the point of view of the chip's design complexity, in 2010, 16 billion transistors could be integrated in 32-nanometer chips, the most critical of which is that due to the smaller and smaller chips, their variability allows designers to It's getting harder to verify. In terms of production efficiency, each design engineer has to design an average of 1.2 million circuits in one year in 2009. By 2021, this number will reach 32 million. This huge gap needs to be supplemented by increasing production efficiency.
Moreover, in the timing analysis, especially the design of 28 nm and below, the design that requires a variety of different timing scenarios is becoming more and more common. The so-called timing scenario analysis is a combination of voltage, temperature and other process corners x timing modes. "A lot of years ago, the chip may have only two timing modes, the general mode and the test mode. Today, mobile phones and other products may have 5 to 10 timing modes, such as standby, low speed, low power consumption, high speed, etc. Therefore, the designer needs There are as many as 10 to 20 time-sequence scenarios verified,†said Mr. Robert Smith. “That is not surprising, because by the time 22 nanometers, designers will verify that there will be close to 100 time-series scenarios. This is a very difficult technical issue. "Because of limitations in the ability to analyze timing scenarios, companies generally choose only some of the timing scenarios that are the most problematic.
From objective needs, more efficient timing analysis tools are needed. And Magma's latest Talus1.2 can manage five times more time-series scenarios than traditional solutions, while also providing 10 times the runtime improvement.
At the same time, Magma offers TalusVortexFX, which has a 3X performance improvement over Talus1.2.
In an analysis table, the reporter saw the first iPhone-based platform clocked at 620MHz, with 128MbRAM, and has a 2 million-pixel camera and 3-axis accelerometer; and the iPhone 4 launched in 2010, the platform clock speed Has risen to 800MHz, RAM reached 512Mb, while having 30 frames per second HD video recording and 3-axis gyroscope / digital compass function. "I was very surprised to have so many features integrated in such a small package," said Robert Smith. "In order to integrate more features in a smaller area, advanced IC design companies have already turned to 32-nanometer and 28-nanometer technologies. At present, five advanced IC design companies are using Magma's tools to develop 28nm products, and the pressure facing IC design companies is conceivable."
The cost, complexity, and production efficiency of the chip are three things IC design companies typically face. Unfortunately, the development of these three factors at 32-nm, 28-nm, and smaller node designs has caused everyone to find it tricky. From a design cost point of view, the cost of a 32-nanometer chip design is around 70 million U.S. dollars. It will soar to 100 million U.S. dollars at 28 nanometers, and it will increase to 120 to 150 million U.S. dollars at 20 nanometers. At the same time, from the point of view of the chip's design complexity, in 2010, 16 billion transistors could be integrated in 32-nanometer chips, the most critical of which is that due to the smaller and smaller chips, their variability allows designers to It's getting harder to verify. In terms of production efficiency, each design engineer has to design an average of 1.2 million circuits in one year in 2009. By 2021, this number will reach 32 million. This huge gap needs to be supplemented by increasing production efficiency.
Moreover, in the timing analysis, especially the design of 28 nm and below, the design that requires a variety of different timing scenarios is becoming more and more common. The so-called timing scenario analysis is a combination of voltage, temperature and other process corners x timing modes. "A lot of years ago, the chip may have only two timing modes, the general mode and the test mode. Today, mobile phones and other products may have 5 to 10 timing modes, such as standby, low speed, low power consumption, high speed, etc. Therefore, the designer needs There are as many as 10 to 20 time-sequence scenarios verified,†said Mr. Robert Smith. “That is not surprising, because by the time 22 nanometers, designers will verify that there will be close to 100 time-series scenarios. This is a very difficult technical issue. "Because of limitations in the ability to analyze timing scenarios, companies generally choose only some of the timing scenarios that are the most problematic.
From objective needs, more efficient timing analysis tools are needed. And Magma's latest Talus1.2 can manage five times more time-series scenarios than traditional solutions, while also providing 10 times the runtime improvement.
At the same time, Magma offers TalusVortexFX, which has a 3X performance improvement over Talus1.2.
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